GD112
7 Port Multidrop IEEE1149.1 (JTAG) Multiplexer
Applications :
- JTAG Scan Chain Multiplexing
- System Level JTAG Test and Programming
- Hierarchical and Multidrop JTAG Scan Chain Management
Description
The GD112 provides a 7 port IEEE1149.1 (JTAG) multiplexer along with mutidrop addressable capability. The multiplexer enables the 7 local scan ports to partition a scan chain to enable simplification and execution time reduction of the test and programming sequences. The inclusion and omission of optional daughter cards and ICs can be supported in dedicated local scan ports. The GD112 enables the 7 local scan ports to be selected separately or in any combination as required.
The multidrop addressable capabilities enable operation on a backplane with other GD112s or other devices with a similar addressable scheme.
The GD112 device provides the standard selection method where the 8 address input pins are compared to the value loaded in the instruction register. It is also possible to enable and disable a further selection criteria to the GD112 selection protocol, utilising the selection packet engine overcomes issues when using debug tool in a backplane environment.
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GLD2 : Generic (JTAG) Linker Device
Features
- ATPG support in all major software vendor tools
- Functionally compatible with Lattice Semiconductor BSCAN2 reference design
- Small LUT count in programmable logic device
- High TCK rate achievable
- Customisation of functionality
Overview
The GLD2 provides 4 or more IEEE1149.1 (JTAG) ports that can be multiplexed to a single master port. By providing multiple local scan ports that can be omitted or included into the active scan chain the GLD2 provides the ability to symplify the JTAG architecture on the PCBA and reduce the test execution times.
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Digital Development Consultants provides design services for FPGA and ASIC’s using industry standard languages and tool flows. The engineering staff at Digital Development Consultants, have over 20 years of experience in the design of I.P. for both FPGA’s and ASIC devices, with many completed projects.
A particular area of expertise is in the field of DFT (design for test) solutions, using the IEEE1149.x standard also known as JTAG along with other IEEE standards such as 1687, P2654 etc. Support for testing of SPI and I2C bus interfaces, along with high speed programing of devices on these bus’s. This enables both a reduction in manufacturing cost /time per unit, along with the re-use of factory tests within the field environment by either embedding the tests within the unit or remote test execution.
Digital Development Consultants provides hardware solutions that reduce the time taken for manufacturing tests using traditional ICT and “Boundary scan”. The hardware test solutions can be used standalone to provide a low cost portable test platform or embedded into tests fixtures for use within the ICT flow.
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Digital Development Consultants
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